  O   8     (              L                             (    mediatek,mt8183-pumpkin mediatek,mt8183                                  +            7Pumpkin MT8183     aliases          =/soc/i2c@11007000            B/soc/i2c@11011000            G/soc/i2c@11009000            L/soc/i2c@1100f000            Q/soc/i2c@11008000            V/soc/i2c@11016000            [/soc/i2c@11005000            `/soc/i2c@1101a000            e/soc/i2c@1101b000            j/soc/i2c@11014000            o/soc/i2c@11015000            u/soc/i2c@11017000            {/soc/ovl@14008000            /soc/ovl@14009000            /soc/ovl@1400a000            /soc/rdma@1400b000           /soc/rdma@1400c000           /soc/serial@11002000          cpus                         +       cpu-map    cluster0       core0                     core1                     core2                     core3                        cluster1       core0                     core1                     core2                     core3               	            cpu@0            cpu           arm,cortex-a53                        psci                           
               T                                       cpu@1            cpu           arm,cortex-a53                       psci                           
               T                                       cpu@2            cpu           arm,cortex-a53                       psci                           
               T                                       cpu@3            cpu           arm,cortex-a53                       psci                           
               T                                       cpu@100          cpu           arm,cortex-a73                       psci                            
                                                      cpu@101          cpu           arm,cortex-a73                      psci                            
                                                      cpu@102          cpu           arm,cortex-a73                      psci                            
                                                      cpu@103          cpu           arm,cortex-a73                      psci                            
                                                	      idle-states         &psci       cpu-sleep             arm,idle-state           3        D          [           l           |              
      cluster-sleep-0           arm,idle-state           3        D         [           l          |                   cluster-sleep-1           arm,idle-state           3        D         [           l          |                         opp_table0            operating-points-v2                     ?   opp-300000000                         	h P      opp-320000000                         	 P      opp-340000000               C          	< P      opp-360000000               u*          	Ҧ P      opp-380000000               W          	 P      opp-400000000               ׄ          
z P      opp-420000000                         
 P      opp-460000000               k          
L P      opp-500000000               e          
} P      opp-540000000                /          
` P      opp-580000000               "          
4 P      opp-620000000               $s           P      opp-653000000               &@         YF P      opp-698000000               )          A      opp-743000000               ,IG          6      opp-800000000               /           H         pmu-a53           arm,cortex-a53-pmu                                        pmu-a73           arm,cortex-a73-pmu                                        psci              arm,psci-1.0             smc       fixed-factor-clock-13m            fixed-factor-clock                                                       clk13m                   oscillator            fixed-clock                             clk26m                   timer             arm,armv8-timer                   @                                               
             soc                      +             simple-bus              soc_data@8000000          %    mediatek,mt8183-efuse mediatek,efuse                                                +         	  disabled          interrupt-controller@c000000              arm,gic-v3                                  #      P                                   @              A             B                        	                     ppi-partitions     interrupt-partition-0           8                             interrupt-partition-1           8            	                       syscon@c530000            mediatek,mt8183-mcucfg syscon                S                          interrupt-controller@c530a80          .    mediatek,mt8183-sysirq mediatek,mt6577-sysirq            #                                    S
       P                 syscon@10000000            mediatek,mt8183-topckgen syscon                                                    syscon@10001000            mediatek,mt8183-infracfg syscon                                          A                    syscon@10003000           mediatek,mt8183-pericfg syscon                0                              4      pinctrl@10005000              mediatek,mt8183-pinctrl               P                                                                                                                                   D  Niocfg0 iocfg1 iocfg2 iocfg3 iocfg4 iocfg5 iocfg6 iocfg7 iocfg8 eint          X        h           t                       #                                           i2c0               &   pins_i2c              R  S                                i2c1               0   pins_i2c              Q  T                                i2c2               (   pins_i2c              g  h                                i2c3               /   pins_i2c              2  3                                i2c4               '   pins_i2c              i  j                                i2c5               1   pins_i2c              0  1                                i2c6               %   pins_cmd_dat              q  r                    mmc0-pins-default              5   pins_cmd_dat          $    {    }    ~        z                                     pins_clk              |                      
      pins_rst                                             mmc0-pins-uhs              6   pins_cmd_dat          $    {    }    ~        z                                     pins_clk              |                      
      pins_ds                                 
      pins_rst                                             mmc1-pins-default              9   pins_cmd_dat                   "  !                      
      pins_clk                                  
      pins_pmu                                 mmc1-pins-uhs              :   pins_cmd_dat                   "  !                                 
      pins_clk                                    
                     syscon@10006000           syscon simple-mfd                 `                      power-controller          !    mediatek,mt8183-power-controller                         +                          .   power-domain@0                                   /      7        audio audio1 audio2                   power-domain@1                                           power-domain@2                                    mfg                      +                  power-domain@3                                   +                       )      power-domain@4                                power-domain@5                                power-domain@6                                                 power-domain@7                    X                                                                     	      5  mm mm-0 mm-1 mm-2 mm-3 mm-4 mm-5 mm-6 mm-7 mm-8 mm-9                       7                        +                  power-domain@8                    @                     	                                    .  cam cam-0 cam-1 cam-2 cam-3 cam-4 cam-5 cam-6                      7                     power-domain@9              	              "      	              isp isp-0 isp-1                    7                     power-domain@10             
        7                     power-domain@11                     7                     power-domain@12                   @        &      #                                           -  vpu vpu1 vpu-0 vpu-1 vpu-2 vpu-3 vpu-4 vpu-5                       7                        +                  power-domain@13                           $        vpu2                                 power-domain@14                           %        vpu3                                             watchdog@10007000             mediatek,mt8183-wdt               p                A         syscon@1000c000       "    mediatek,mt8183-apmixedsys syscon                                               *      pwrap@1000d000            mediatek,mt8183-pwrap                                 Npwrap                                   )            	  spi wrap       mt6358            mediatek,mt6358          #                                        mt6358codec           mediatek,mt6358-sound         mt6358regulator           mediatek,mt6358-regulator      buck_vdram1         Dvdram1          S          k L          0                                          buck_vcore          Dvcore           S          k           j                                         buck_vpa            Dvpa         S          k 7          P                                buck_vproc11            Dvproc11         S          k           j                                                    buck_vproc12            Dvproc12         S          k           j                                                    buck_vgpu           Dvgpu            S          k           j                                           buck_vs2            Dvs2         S          k L          0                           buck_vmodem         Dvmodem          S          k           j                                        buck_vs1            Dvs1         S B@        k '{l          0                           ldo_vdram2          Dvdram2          S 	'        k w@                ldo_vsim1           Dvsim1           S         k /M`                ldo_vibr            Dvibr            S O        k 2Z           <      ldo_vrf12             regulator-fixed         Dvrf12           S O        k O           x      ldo_vio18             regulator-fixed         Dvio18           S w@        k w@          
                    8      ldo_vusb            Dvusb            S -        k /M`                         ldo_vcamio            regulator-fixed         Dvcamio          S w@        k w@          E      ldo_vcamd           Dvcamd           S         k w@          E      ldo_vcn18             regulator-fixed         Dvcn18           S w@        k w@                ldo_vfe28             regulator-fixed         Dvfe28           S *        k *                ldo_vsram_proc11            Dvsram_proc11            S          k           j                          ldo_vcn28             regulator-fixed         Dvcn28           S *        k *                ldo_vsram_others            Dvsram_others            S          k           j                          ldo_vsram_gpu         
  Dvsram_gpu           S          k           j                      @      ldo_vxo22             regulator-fixed         Dvxo22           S !        k !           x               ldo_vefuse          Dvefuse          S         k                 ldo_vaux18            regulator-fixed         Dvaux18          S w@        k w@                ldo_vmch            Dvmch            S ,@         k 2Z           <           ;      ldo_vbif28            regulator-fixed         Dvbif28          S *        k *                ldo_vsram_proc12            Dvsram_proc12            S          k           j                          ldo_vcama1          Dvcama1          S w@        k -          E      ldo_vemc            Dvemc            S ,@         k 2Z           <           7      ldo_vio28             regulator-fixed         Dvio28           S *        k *                ldo_va12              regulator-fixed         Dva12            S O        k O                         ldo_vrf18             regulator-fixed         Dvrf18           S w@        k w@           x      ldo_vcn33_bt          	  Dvcn33_bt            S 2Z        k 5g                ldo_vcn33_wifi          Dvcn33_wifi          S 2Z        k 5g                ldo_vcama2          Dvcama2          S w@        k -          E      ldo_vmc         Dvmc         S w@        k 2Z           <           <      ldo_vldo28          Dvldo28          S *        k -                ldo_vaud28            regulator-fixed         Dvaud28          S *        k *                ldo_vsim2           Dvsim2           S         k /M`                   mt6358rtc             mediatek,mt6358-rtc             scp@10500000              mediatek,mt8183-scp               P             \             	  Nsram cfg                                            main                       okay          timer@10017000        ,    mediatek,mt8183-timer mediatek,mt6765-timer              p                                           iommu@10205000            mediatek,mt8183-m4u               P                                               !   "   #   $                      B      mailbox@10238000              mediatek,mt8183-gce              #       @                           
                         gce            A      auxadc@11001000       .    mediatek,mt8183-auxadc mediatek,mt8173-auxadc                                       #        main                       okay               )      serial@11002000       *    mediatek,mt8183-uart mediatek,mt6577-uart                                         [                          	  baud bus            okay          serial@11003000       *    mediatek,mt8183-uart mediatek,mt6577-uart                 0                       \                          	  baud bus          	  disabled          serial@11004000       *    mediatek,mt8183-uart mediatek,mt6577-uart                 @                       ]                          	  baud bus          	  disabled          i2c@11005000              mediatek,mt8183-i2c                P                                    W                 W      *      	  main dma                                    +            okay            (default         6   %               i2c@11007000              mediatek,mt8183-i2c                p                                    Q                 
      *      	  main dma                                    +            okay            (default         6   &               i2c@11008000              mediatek,mt8183-i2c                                                    R                       *      G        main dma arb                                    +            okay            (default         6   '               i2c@11009000              mediatek,mt8183-i2c                                                   S                       *      I        main dma arb                                    +            okay            (default         6   (               spi@1100a000              mediatek,mt8183-spi                      +                                         x                 6                    parent-clk sel-clk spi-clk        	  disabled          thermal@1100b000            @             mediatek,mt8183-thermal                                     	      #        therm auxadc            V                      L           ]   )        m   *           +        calibration-data               ,      thermal-zones      cpu_thermal            d                     ,                 trips      trip-point0          	                   passive       trip-point1          8                   passive            -      cpu-crit             8                	   critical             cooling-maps       map0               -      0                                map1               -      0               	                       tzts1                                      ,                trips         cooling-maps             tzts2                                      ,                trips         cooling-maps             tzts3                                      ,                trips         cooling-maps             tzts4                                      ,                trips         cooling-maps             tzts5                                      ,                trips         cooling-maps             tztsABB                                    ,                trips         cooling-maps                pwm@1100e000              mediatek,mt8183-disp-pwm                                                       .           *                       5        main mm       pwm@11006000              mediatek,mt8183-pwm               `                *         0                                              top main pwm1 pwm2 pwm3 pwm4          i2c@1100f000              mediatek,mt8183-i2c                                                    T                       *      	  main dma                                    +            okay            (default         6   /               spi@11010000              mediatek,mt8183-spi                      +                                         |                 6            8        parent-clk sel-clk spi-clk        	  disabled          i2c@11011000              mediatek,mt8183-i2c                                                  U                 9      *      	  main dma                                    +            okay            (default         6   0               spi@11012000              mediatek,mt8183-spi                      +                                                          6            ;        parent-clk sel-clk spi-clk        	  disabled          spi@11013000              mediatek,mt8183-spi                      +                 0                                        6            <        parent-clk sel-clk spi-clk        	  disabled          i2c@11014000              mediatek,mt8183-i2c               @                                                    H      *      G        main dma arb                                    +          	  disabled          i2c@11015000              mediatek,mt8183-i2c               P                                                     J      *      I        main dma arb                                    +          	  disabled          i2c@11016000              mediatek,mt8183-i2c               `                                    V                 D      *      E        main dma arb                                    +            okay            (default         6   1               i2c@11017000              mediatek,mt8183-i2c               p                                                    F      *      E        main dma arb                                    +          	  disabled          spi@11018000              mediatek,mt8183-spi                      +                                                         6            K        parent-clk sel-clk spi-clk        	  disabled          spi@11019000              mediatek,mt8183-spi                      +                                                         6            L        parent-clk sel-clk spi-clk        	  disabled          i2c@1101a000              mediatek,mt8183-i2c                                                  X                 b      *      	  main dma                                    +          	  disabled          i2c@1101b000              mediatek,mt8183-i2c                                                   Y                 c      *      	  main dma                                    +          	  disabled          usb@11201000          #    mediatek,mt8183-mtu3 mediatek,mtu3                        .      >              	  Nmac ippc                   H           5   2      3                 =      Z        sys_ck ref_ck           :   4      e                     +                  	  disabled       usb@11200000          '    mediatek,mt8183-xhci mediatek,mtk-xhci                                 Nmac                I                 =      Z        sys_ck ref_ck         	  disabled             syscon@11220000            mediatek,mt8183-audiosys syscon              "                          mmc@11230000              mediatek,mt8183-mmc               #                                     M                                     source hclk source_cg           okay            (default state_uhs           6   5        Q   6        [           e          s                                                      (           7           8                            U               mmc@11240000              mediatek,mt8183-mmc               $                                     N                 	            (        source hclk source_cg           okay            (default state_uhs           6   9        Q   :        [           e                   0         =         K         X                    ;           <         _         u               dsi-phy@11e50000              mediatek,mt8183-mipi-tx                                  *                                   mipi_tx0_pll               =        calibration-data               C      efuse@11f10000        %    mediatek,mt8183-efuse mediatek,efuse                                               +      calib@180                            +      calib@190                            =         t-phy@11f40000        .    mediatek,mt8183-tphy mediatek,generic-tphy-v2                        +                                okay       usb-phy@0                                      ref                               okay               2      usb-phy@700               	                    ref                    okay               3         syscon@13000000           mediatek,mt8183-mfgcfg syscon                                                >      gpu@13040000          &    mediatek,mt8183-mali arm,mali-bifrost                        @       $                                     job mmu gpu            >               .      .      .           core0 core1 core2              ?                      @      syscon@14000000           mediatek,mt8183-mmsys syscon                                                 A          A                 A                           ovl@14008000              mediatek,mt8183-disp-ovl                                                       .                            B                          A               ovl@14009000              mediatek,mt8183-disp-ovl-2l                                                    .                            B                         A               ovl@1400a000              mediatek,mt8183-disp-ovl-2l                                                    .                            B                         A               rdma@1400b000             mediatek,mt8183-disp-rdma                                                      .                            B                      &              A               rdma@1400c000             mediatek,mt8183-disp-rdma                                                      .                            B                      &              A               color@1400e000        6    mediatek,mt8183-disp-color mediatek,mt8173-disp-color                                                      .                            A               ccorr@1400f000            mediatek,mt8183-disp-ccorr                                                     .                            A               aal@14010000          2    mediatek,mt8183-disp-aal mediatek,mt8173-disp-aal                                                      .                            A                gamma@14011000            mediatek,mt8183-disp-gamma                                                    .                            A               dither@14012000           mediatek,mt8183-disp-dither                                                    .                            A                dsi@14014000              mediatek,mt8183-dsi              @                                     .           >     @                        C        engine digital hs           5   C        Rdphy          	  disabled          mutex@14016000            mediatek,mt8183-disp-mutex               `                                     .           \            larb@14017000             mediatek,mt8183-smi-larb                 p                7                                  .           apb smi                  smi@14019000              mediatek,mt8183-smi-common                                                                  apb smi gals0 gals1            .                    syscon@15020000           mediatek,mt8183-imgsys syscon                                                     larb@15021000             mediatek,mt8183-smi-larb                                 7                 	      	              apb smi gals               .   	           #      larb@1502f000             mediatek,mt8183-smi-larb                                 7                             	        apb smi gals               .   	                  syscon@16000000           mediatek,mt8183-vdecsys syscon                                               D      larb@16010000             mediatek,mt8183-smi-larb                                  7              D       D           apb smi            .   
                 syscon@17000000           mediatek,mt8183-vencsys syscon                                               E      larb@17010000             mediatek,mt8183-smi-larb                                  7              E       E            apb smi            .              "      syscon@19000000            mediatek,mt8183-ipu_conn syscon                                                    syscon@19010000           mediatek,mt8183-ipu_adl syscon                                         syscon@19180000       !    mediatek,mt8183-ipu_core0 syscon                                           syscon@19280000       !    mediatek,mt8183-ipu_core1 syscon                 (                          syscon@1a000000           mediatek,mt8183-camsys syscon                                                      larb@1a001000             mediatek,mt8183-smi-larb                                  7                                       apb smi gals               .              $      larb@1a002000             mediatek,mt8183-smi-larb                                   7                 	      	              apb smi gals               .              !         memory@40000000          memory               @                chosen          pserial0:921600n8          reserved-memory                      +               scp_mem_region@50000000           shared-dma-pool              P                  |                    leds          
    gpio-leds      led-red         red                           off       led-green           green                             off          ntc           murata,ncp03wf104            w@         p                       )             	compatible interrupt-parent #address-cells #size-cells model i2c0 i2c1 i2c2 i2c3 i2c4 i2c5 i2c6 i2c7 i2c8 i2c9 i2c10 i2c11 ovl0 ovl-2l0 ovl-2l1 rdma0 rdma1 serial0 cpu device_type reg enable-method capacity-dmips-mhz cpu-idle-states dynamic-power-coefficient #cooling-cells proc-supply phandle entry-method local-timer-stop arm,psci-suspend-param entry-latency-us exit-latency-us min-residency-us opp-shared opp-hz opp-microvolt interrupts #clock-cells clocks clock-div clock-mult clock-output-names clock-frequency ranges status #interrupt-cells interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges pinmux mediatek,pull-up-adv mediatek,drive-strength-adv input-enable drive-strength mediatek,pull-down-adv output-high #power-domain-cells clock-names mediatek,infracfg domain-supply mediatek,smi regulator-name regulator-min-microvolt regulator-max-microvolt regulator-ramp-delay regulator-enable-ramp-delay regulator-always-on regulator-allowed-modes memory-region mediatek,larbs #iommu-cells #mbox-cells #io-channel-cells pinctrl-names pinctrl-0 #thermal-sensor-cells resets mediatek,auxadc mediatek,apmixedsys nvmem-cells nvmem-cell-names polling-delay-passive polling-delay thermal-sensors sustainable-power temperature hysteresis trip cooling-device contribution power-domains #pwm-cells phys mediatek,syscon-wakeup pinctrl-1 bus-width max-frequency cap-mmc-highspeed mmc-hs200-1_8v mmc-hs400-1_8v cap-mmc-hw-reset no-sdio no-sd hs400-ds-delay vmmc-supply vqmmc-supply assigned-clocks assigned-clock-parents non-removable cap-sd-highspeed sd-uhs-sdr50 sd-uhs-sdr104 cap-sdio-irq no-mmc keep-power-in-suspend enable-sdio-wakeup #phy-cells mediatek,discth interrupt-names power-domain-names operating-points-v2 mali-supply sram-supply mboxes mediatek,gce-client-reg iommus mediatek,larb mediatek,rdma-fifo-size mediatek,syscon-dsi phy-names mediatek,gce-events stdout-path no-map label gpios default-state pullup-uv pullup-ohm pulldown-ohm io-channels 