  (D   8  &P   (              &                             $    mediatek,mt8192-evb mediatek,mt8192                                  +         !   7MediaTek MT8192 evaluation board       oscillator0           fixed-clock          =             J         Zclk26m           m         oscillator1           fixed-clock          =             J            Zclk32k        cpus                         +       cpu@0            ucpu           arm,cortex-a55                        psci             Jec3@                                               m         cpu@100          ucpu           arm,cortex-a55                       psci             Jec3@                                               m   	      cpu@200          ucpu           arm,cortex-a55                       psci             Jec3@                                               m   
      cpu@300          ucpu           arm,cortex-a55                       psci             Jec3@                                               m         cpu@400          ucpu           arm,cortex-a76                       psci             Jf                                                m         cpu@500          ucpu           arm,cortex-a76                       psci             Jf                                                m         cpu@600          ucpu           arm,cortex-a76                       psci             Jf                                                m         cpu@700          ucpu           arm,cortex-a76                       psci             Jf                                                m         cpu-map    cluster0       core0                     core1               	      core2               
      core3                        cluster1       core0                     core1                     core2                     core3                           l2-cache0             cache                        m         l2-cache1             cache                        m         l3-cache              cache            m         idle-states       	   arm,psci       cpuoff_l              arm,idle-state                                   7                   !           m         cpuoff_b              arm,idle-state                                   #                   !           m         clusteroff_l              arm,idle-state                                  <                   !  \         m         clusteroff_b              arm,idle-state                                  (                   !           m               pmu-a55           arm,cortex-a55-pmu                      2                  pmu-a76           arm,cortex-a76-pmu                      2                  psci              arm,psci-1.0             smc       timer             arm,armv8-timer                   @  2                                             
                J ]@      soc                      +             simple-bus           =   interrupt-controller@c000000              arm,gic-v3          D           U                        l                                              2      	                m      ppi-partitions     interrupt-partition-0                 	   
            m         interrupt-partition-1                                m               pinctrl@10005000              mediatek,mt8192-pinctrl               P                                                                                                                                                ]  iocfg0 iocfg_rm iocfg_bm iocfg_bl iocfg_br iocfg_lm iocfg_lb iocfg_rt iocfg_lt iocfg_tl eint                                                       l        2                      D            m         timer@10017000        ,    mediatek,mt8192-timer mediatek,mt6765-timer              p                2                                 clk13m        serial@11002000       *    mediatek,mt8192-uart mediatek,mt6577-uart                                  2       m                           	  baud bus            okay          serial@11003000       *    mediatek,mt8192-uart mediatek,mt6577-uart                 0                2       n                           	  baud bus          	  disabled          spi@1100a000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +                                  2                                       parent-clk sel-clk spi-clk        	  disabled          spi@11010000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +                                  2                                       parent-clk sel-clk spi-clk        	  disabled          spi@11012000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +                                  2                                       parent-clk sel-clk spi-clk        	  disabled          spi@11013000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +                 0                2                                       parent-clk sel-clk spi-clk        	  disabled          spi@11018000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +                                 2                                       parent-clk sel-clk spi-clk        	  disabled          spi@11019000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +                                 2                                       parent-clk sel-clk spi-clk        	  disabled          spi@1101d000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +                                 2                                       parent-clk sel-clk spi-clk        	  disabled          spi@1101e000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +                                 2                                       parent-clk sel-clk spi-clk        	  disabled          spi@11234000              mediatek,mt8192-nor              #@                2                                      spi sf axi                       +          	  disabled          i2c3@11cb0000             mediatek,mt8192-i2c                            !s                2       s                           	  main dma                                    +          	  disabled          i2c7@11d00000             mediatek,mt8192-i2c                            !v               2       w                           	  main dma                                    +          	  disabled          i2c8@11d01000             mediatek,mt8192-i2c                           !w              2       x                           	  main dma                                    +          	  disabled          i2c9@11d02000             mediatek,mt8192-i2c                            !y               2       y                           	  main dma                                    +          	  disabled          i2c1@11d20000             mediatek,mt8192-i2c                            !q                2       q                           	  main dma                                    +          	  disabled          i2c2@11d21000             mediatek,mt8192-i2c                           !q              2       r                           	  main dma                                    +          	  disabled          i2c4@11d22000             mediatek,mt8192-i2c                            !s              2       t                           	  main dma                                    +          	  disabled          i2c5@11e00000             mediatek,mt8192-i2c                            !u                2       u                           	  main dma                                    +          	  disabled          i2c0@11f00000             mediatek,mt8192-i2c                            !p               2       p                           	  main dma                                    +          	  disabled          i2c6@11f01000             mediatek,mt8192-i2c                           !u               2       v                           	  main dma                                    +          	  disabled             aliases         /soc/serial@11002000          chosen          serial0:921600n8          memory@40000000          umemory               @                   	compatible interrupt-parent #address-cells #size-cells model #clock-cells clock-frequency clock-output-names phandle device_type reg enable-method cpu-idle-states next-level-cache capacity-dmips-mhz cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us interrupts ranges #interrupt-cells #redistributor-regions interrupt-controller affinity reg-names gpio-controller #gpio-cells gpio-ranges clocks clock-names status clock-div serial0 stdout-path 