Ðþí  Ö   8  
ä   (             ò  
¬                             $    mediatek,mt6795-evb mediatek,mt6795                                  +         !   7MediaTek MT6795 Evaluation Board       psci              arm,psci-0.2             =smc       cpus                         +       cpu@0            Dcpu           arm,cortex-a53           Ppsci             ^          cpu@1            Dcpu           arm,cortex-a53           Ppsci             ^         cpu@2            Dcpu           arm,cortex-a53           Ppsci             ^         cpu@3            Dcpu           arm,cortex-a53           Ppsci             ^         cpu@100          Dcpu           arm,cortex-a53           Ppsci             ^         cpu@101          Dcpu           arm,cortex-a53           Ppsci             ^        cpu@102          Dcpu           arm,cortex-a53           Ppsci             ^        cpu@103          Dcpu           arm,cortex-a53           Ppsci             ^           dummy13m              fixed-clock          b Æ]@         r          dummy32k              fixed-clock          b  }          r          dummy26m              fixed-clock          bŒº€         r                      timer             arm,armv8-timer                   0   ‡        ÿ        ÿ        ÿ      
  ÿ      intpol-controller@10200620        .    mediatek,mt6795-sysirq mediatek,mt6577-sysirq             ’         §                        ^                                interrupt-controller@10221000             arm,gic-400          §                         ’      @   ^    "            "              "@             "`                           serial@11002000       *    mediatek,mt6795-uart mediatek,mt6577-uart            ^                       ‡       [            ¸            ¿okay          serial@11003000       *    mediatek,mt6795-uart mediatek,mt6577-uart            ^     0                 ‡       \            ¸         	   ¿disabled          serial@11004000       *    mediatek,mt6795-uart mediatek,mt6577-uart            ^     @                 ‡       ]            ¸         	   ¿disabled          serial@11005000       *    mediatek,mt6795-uart mediatek,mt6577-uart            ^     P                 ‡       ^            ¸         	   ¿disabled          aliases          Æ/serial@11002000             Î/serial@11003000             Ö/serial@11004000             Þ/serial@11005000          memory@40000000          Dmemory           ^    @       €        chosen           æserial0:921600n8             	compatible interrupt-parent #address-cells #size-cells model method device_type enable-method reg clock-frequency #clock-cells phandle interrupts interrupt-controller #interrupt-cells clocks status serial0 serial1 serial2 serial3 stdout-path 